A semiconductor device such as, for example, a field effect transistor, is often formed with both back end of the line (BEOL) contacts to the gate and source/drain regions of the device to turn the device on/off and to allow current to flow through the device, respectively, and a middle of the line (MOL) contact to the body of the device between the source/drain regions to adjust threshold voltage (Vt).
Traditionally, conductive metals, such as tungsten (W) and aluminum (Al) have been deposited (e.g., by chemical vapor deposition (CVD), sputtering, etc.) into patterned openings (i.e., vias), which are present in the dielectric material of the contact (i.e., metallization) structure, to form both MOL and BEOL contacts. Recently, because of its lower electrical resistivity copper and copper alloys, which require plating, have become the preferred metal for filling the contact openings in both BEOL and MOL contact (i.e., metallization) structures.
Forming contact structures that include vias that are filled with such conductive metals to the source/drain regions and the gate of field effect transistors populated using tight pitch design rules introduce process and material challenges. For example, it was predicted that 20-30 nm vias will show a substantial increase on resistance due to via sidewall roughness and an increase on the filling conductive resistivity. Overcoming the increased conductor resistivity and the need to maintain smooth via sidewalls led to a proposal in which the via conductor will be replaced by bundles of carbon nanotubes (CNTs). While carbon nanotubes were shown to have excellent conduction properties, their integration is challenging. For example, the typical synthesis temperature for carbon nanotubes is above 700° C., which is much higher than the limit of 400° C. imposed by BEOL technology. Additionally, BEOL processes such as photoresist removal by O2 plasma and some PECVD dielectric depositions cannot be carried out in the presence of carbon nanotubes. Furthermore, forming a good contact between the silicide (at the bottom of the via) and the CNTs, and similarly between the metal (at the top of the via) and the CNTs is challenging. Avoiding the contact resistance between two different materials, i.e., the via conductor and the silicide, can further reduce the total access resistance to the device being contacted.